1. Field of the Invention
This invention relates generally to flash EEPROM cells, and more particularly to a method of programming and erasing EEPROM cells.
2. Description of Related Art
Erasable read-only memory cells, widely known as EPROMs, are a versatile type of nonvolatile semiconductor memory. A typical N-channel EPROM cell is composed of an N-channel silicon-gate storage transistor which uses a floating first layer polysilicon gate (floating gate), which is directly accessed via a second stacked polysilicon gate (control gate), to trap and store electrons for extremely long periods of time.
The N-channel EPROM cell is considered to be in a programmed state when the floating gate has a net negative charge due to the presence of "hot electrons" injected from the drain. When the cell is in a programmed state, the electrons on the floating gate keep the N-channel transistor in a logical off state.
Conversely, the cell is considered to be in an erased state when there are no electrons on the floating gate and thus no net negative charge on the gate. To erase the cell, the energy of the electrons stored on the floating gate is raised until the electrons can "tunnel" through the tunnel dielectric from the gate to the source, a phenomenon commonly known as Fowler-Nordheim tunneling. When the cell is erased, the N-channel transistor is in a logical on state. Note that N-channel EPROMs are preferred over P-channel EPROMs due to the programmability and speed advantages of N-channel EPROMs.
EPROMs are conventionally UV-erasable. That is, to erase the cell, relatively high-intensity ultraviolet light is used to excite floating gate electrons and cause them to move off the gate. There are a number of disadvantages with UV-erasable EPROMs. For example, such cells require the use of costly clear quartz windows to allow for UV irradiation of the floating gates. Additionally, the entire array of exposed EPROM cells is erased, even when it is desired to erase only a few cells. To overcome shortcomings such as these, flash electrically erasable read-only memory, widely known as flash EEPROMs, were developed.
Flash EEPROMs typically use Fowler-Nordheim tunneling, as opposed to hot-electron injection, for cell programming as well as for cell erase. A voltage signal, usually less than 25 volts, is applied to the control gate, which is capacitively coupled to the floating gate, while the drain is held either at ground potential or at a voltage less than that applied to the control gate, and the source is held at ground potential. Under such conditions, Fowler-Nordheim tunneling occurs, in which electrons from the drain, tunnel through a thin layer of SiO.sub.2 (tunnel dielectric) to the floating gate.
An important difference between EEPROMs and EPROMs is in the way in which the cells are erased, or more specifically, the way in which the floating gate electrons are removed. Unlike UV-erasable EPROMs, a conventional EEPROM cell electrically induces Fowler-Nordheim electron tunneling to erase the floating polysilicon gate. A voltage signal, typically less than 25 volts, is applied to the cell drain while the control gate is held at ground potential and the source is left at a floating, or unspecified, voltage potential. As a result, the electrons stored on the floating gate will tunnel through the tunnel dielectric to the source.
An advantage of electrical erase over UV erase is that electrical erase can allow for selective erasure of cells in an array, as opposed to erasure of all cells in an array. A conventional EEPROM cell contains an additional "select" gate to control erasure of that cell. By providing a byte-decode transistor for each EEPROM cell in a memory array to control its select gate, selective erase of individual cells or bits in the array can be achieved as opposed to full-array erase in the case of UV-erasable EPROM memory arrays.
Although selective erase can thus be achieved, the additional select gate, for example, causes an EEPROM cell to be somewhat larger than an EPROM cell.
An alternative type of EEPROM cell known as the flash EEPROM cell does not contain an additional select gate and thus is smaller than a conventional EEPROM cell.
However, a memory array of flash EEPROM cells typically cannot be selectively erased due to the absence of select gates. Like an EPROM cell array, all the cells in a flash EEPROM cell array are erased even when not all of the cells in the array need to be erased. Moreover, flash EEPROMs often are more prone to program disturb problems than are conventional EEPROMs due to their different array architecture and absence of byte selection circuitry.
Memory arrays using flash EEPROMs often employ a "chip-mode" program cycle. First, all the cells in the array are programmed (logic off state). Second, all the cells in the array are erased (logic on state). Lastly, individual cells in the array are selectively programmed, while other cells remain in the erased state. Note that all the cells in the memory array are programmed first before they are erased in order to avoid "over-erasing". For an over-erased cell, unselected cells can become leaky leading to incorrect sensing of a selected bit on the same bit line and it will also be difficult to program the bit again.
Chip mode programming suffers from the disadvantage that every time a single cell (data bit) needs to be programmed, the whole chip must undergo the above-described cycle. Accordingly, all the cells must go through at least one program and erase cycle. As a result, some cells are unnecessarily cycled, i.e. programmed and erased, leading to unnecessary and premature wearout. Additionally, the average programming time can be unnecessarily long.
In view of the foregoing, it is a general objective of the present invention to provide an improved method for selective erase of flash EEPROM cells.